supertex inc. supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv758 features hvcmos ? technology for high performance high density integration ultrasound transmitter 0 to 90v output voltage 2.2a source and sink current in pw mode 580ma source and sink current in cw mode up to 20mhz operating frequency matched delay times 1.2 to 5.0v cmos logic interface built-in output drain bleed resistors application medical ultrasound imaging piezoelectric transducer drivers ndt ultrasound transmission pulse waveform generator ? ? ? ? ? ? ? ? ? ? ? ? ? general description the supe rt ex hv758 is a four-channel, monolithic high voltage, high speed pulse generator. it is designed for medical ultrasound applications. this high voltage and high speed integrated circuit can also be used for other piezoelectric, capacitive or mems transducers in ultrasonic nondestructive detection and sonar ranger applications. the hv758 comprises a controller logic interface circuit, level translators, mosfet gate drivers and high power p-channel and n-channel mosfets as the output stage for each channel. the output current limit can be set to one of four levels by using two mode control inputs. the output stages of each channel are designed to provide peak output currents over 2.2a when in mode 4, with up to 180v swings. when in mode 1, the output stages reduce the peak current to 580ma for cw mode operation, which reduces the power dissipation of the ic. the power mosfet gate drivers are supplied by two ?oating 10vdc power supplies referenced to v pp and v nn . this direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the pcb layout easier. typical application circuit four-channel, high speed, 90v 2.2a ultrasound pulser nin 1 sub +10v +1.8 to 3.3v logic 0 to +90 v en mc1 c1 0 to -90v txn1 1 of 4 channels c2 c3 c5 c4 txp1 x1 d1 +1.8 to 3.3v +90v c6 c7 en_pwr mc0 otp pin1 rgnd rgnd hv758 p-driver n-driver level translator level translator v pp -10v vpf vdd gref vpp vnn v nn +10v hv out 1 vnf vsub vll vss rp1 rn1 ????????
2 hv758 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ordering information device 64-ball fcbga 8.00x8.00mm body 1.97mm height (max) 0.80mm pitch hv758 HV758FB absolute maximum ratings parameter value v ss , power supply reference 0v v ll , positive logic supply -0.5v to +7.0v v dd , positive logic and level translator supply -0.5v to +14v (v pp - v pf ) positive ?oating gate drive supply -0.5v to +14v (v nf - v nn ) negative gate ?oating drive supply -0.5v to +14v (v pp - v nn ) differential high voltage supply +190v v pp , high voltage positive supply -0.5v to +95v v nn , high voltage negative supply +0.5v to -95v otp, over temperature protection output -0.5v to +7.0v all logic input pin x , nin x and en voltages -0.5v to +7.0v (v sub - v ss ) substrate to v ss voltage difference +190v (v pp - txp x ) v pp to txp x voltage difference +190v (v sub - txp x ) substrate to txp x voltage difference +190v (txn x - v nn ) txn x to v nn voltage difference +190v operating temperature -40c to +125c storage temperature -65c to +150c thermal resistance, ja , (4 layer, 1oz., 4x3, 36-via pcb) 12.8c/w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. power-up sequence step description 1 v sub 2 v ll with logic signal low 3 v dd 4 (v pp - v pf ) and (v nf - v nn ) 5 v pp and v nn 6 logic control signals power-down sequence step description 1 all logic signals go to low 2 v pp and v nn 3 (v pp - v pf ) and (v nf - v nn ) 4 v dd 5 v ll 6 v sub pin con?guration package marking a b c d e f g h 1 2 3 4 5 6 7 8 64-ball fcbga (top view ) yy = year sealed ww = week sealed l = lot number yyww HV758FB lllllllll 64-ball fcbga package may or may not include the following marks: si or 64-ball fcbga (top view) ????????
3 hv758 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com operating supply voltages and current (4 channel active) (operating conditions, unless otherwise speci?ed, v ss = 0v, v ll = +3.3v, v dd = +10v, v pp -v pf = +10v, v nn -v nf = -10v, v pp =+90v, v nn = -90v, t a = 25c) sym parameter min typ max units conditions v ll logic voltage reference 1.2 2.5 5.0 v --- v dd internal voltage supply 7.5 12 12.6 v --- v pf positive gate driver supply (v pp -12.6) (v pp -12) (v pp -7.5) v floating driver voltage supplies equals v dd . v nf negative gate drive supply (v nn +7.5) (v nn +12) (v nn +12.6) v v sub ic substrate voltage v dd v pp +90 v must be the most positive potential of the ic. v pp positive hv supply 0 - +90 v --- v nn negative hv supply -90 - 0 v --- sr max allowable slew rate on v pp, v nn - - 25 v/s --- i ll v ll current en = low - 125 250 a --- i ddq v dd current en = low - 100 - a --- i dden v dd current en = high - 1.1 2.0 ma f = 0mhz i dden v dd current mode = 4 - 3.2 - ma f = 5.0mhz, continuous, no loads i ddencw v dd current mode = 1 - 3.1 - ma i ppq v pp current en = low - 74 90 a f = 0mhz i ppen v pp current mode = 4 - 258 - ma f = 5.0mhz, continuous, no loads i ppencw v pp current mode = 1 - 215 - ma i nnq v nn current en = low - 78 90 a f = 0mhz i nnen v nn current mode = 4 - 258 - ma f = 5.0mhz, continuous, no loads i nnencw v nn current mode = 1 - 215 - ma i pfq v pf current en = low - 37 70 a f = 0mhz i pfen v pf current mode = 4 - 70 - ma f = 5.0mhz, continuous, no loads i pfencw v pf current mode = 1 - 9.0 - ma i nfq v nf current en = low - 35 70 a f = 0mhz i nfen v nf current mode = 4 - 42 - ma f = 5.0mhz, continuous, no loads i nfencw v nf current mode = 1 - 6.0 - ma note: all supply current values are for reference only. under voltage and over temperature protection sym parameter min typ max units conditions v pull_up open drain pull-up voltage - - 5.0 v --- v uvdd v dd threshold 3.5 - 7.0 v --- v uvll v ll threshold 0.7 - 1.0 v --- v uvvf v pf , v nf threshold 3.5 - 7.0 v --- v ol_otp otp ?ag output low voltage - - 1.0 v v ll = 2.5v, otp = active, i pull_up = 1.0ma. i otp max. open drain output current - 1.0 - ma --- t otp over-temperature threshold 95 110 125 c if over-temperature occurred, otp low and all tx outputs will be hiz. t hys otp output reset hysteresis - 7.0 - ????????
4 hv758 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com electrical characteristics (operating conditions, unless otherwise speci?ed, v ss = 0v, v ll = +3.3v, v dd = +10v, v pp -v pf = +10v, v nn -v nf = -10v, v pp =+90v, v nn = -90v, t a = 25c) output p-channel mosfet, txp (mode 4) sym parameter min typ max units conditions i out output saturation current 2.2 2.5 - a --- r on channel resistance - 6.5 - i sd = 100ma c oss output capacitance - 215 - pf v ds = 25v, f = 1.0mhz output n-channel mosfet, txn (mode 4) sym parameter min typ max units conditions i out output saturation current 2.1 2.2 - a --- r on channel resistance - 6.3 - i sd = 100ma c oss output capacitance - 90 - pf v ds = 25v, f = 1.0mhz mosfet drain bleed resistor sym parameter min typ max units conditions r p/n1~4 output bleed resistance 10 15 30 k --- p ro bleed resistors power limit - - 40 mw --- logic inputs sym parameter min typ max units conditions v ih input logic high voltage (v ll -0.4) - v ll v --- v il input logic low voltage 0 - 0.4 v --- i ih input logic high current - - 10 a --- i il input logic low current -10 - - a --- c in input logic capacitance - - 5.0 pf --- ac electrical characteristics (operating conditions, unless otherwise speci?ed, v ss = 0v, v ll = +3.3v, v dd = +10v, v pp -v pf = +10v, v nn -v nf = -10v, v pp = +90v, v nn = -90v, t a = 25c) sym parameter min typ max units conditions t r output rise time - 32 - ns 330pf//2.5k load t f output fall time - 32 - ns f out output frequency range 20 - - mhz 100 resistor load hd2 second harmonic distortion - 30 - db t en enable time - 70 250 s t dr delay time on inputs rise - 18 - ns 2.2 resistor load (see timing diagram) t df delay time on inputs fall - 18 - ns t delay delay time matching - - 3.0 ns p to n, channel to channel t dm delay on mode change - 2.5 20 s --- t j delay jitter on rise or fall - 15 - ps v pp /v nn = +/-25v, input t r 50% to hv out t r or t f 50%, with 330pf//2.5k load ????????
5 hv758 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com switching time diagram 10% 90% pinx nin x output v nn v pp t r 10% t r 90% 0 switch ac test timing diagram t drp 50% pinx nin x t dfp txpx i out 0a txnx 50% 50% 50% nin 1 sub v pf v dd gref en mc1 txn1 v nf 1of n channels txp1 r1 r2 v ll en_pwr mc0 otp vss pin1 rgnd rp1 rn1 rgnd v pp v nn 0a v sub p-driver n-driver level translator level translator t drn t dfn i out ????????
6 hv758 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com a1 corner 1 2 3 4 5 6 7 8 a v pf v pp v pp v nn v nn v nf txn4 txn4 b v pf v pp v pp v nn v nn v nf txp4 txp4 c v dd v sub pin4 nin4 mc0 v sub txn3 txn3 d v ss otp pin3 nin3 mc1 rgnd txp3 txp3 e v ss v ll pin2 nin2 en rgnd txn2 txn2 f v dd v sub pin1 nin1 g ref v sub txp2 txp2 g v pf v pp v pp v nn v nn v nf txn1 txn1 h v pf v pp v pp v nn v nn v nf txp1 txp1 ball con?guration truth table (all modes) logic inputs output en pin x nin x txp x txn x 1 0 0 off off 1 1 0 on off 1 0 1 off on 1 1 1 on* on* 0 x x off off *note: not allowed, may damage ic drive mode control table mode mc1 mc0 i sc (a) r onp () r onr () 1 0 0 0.58 28 27 2 0 1 0.8 20 19.7 3 1 0 1.35 12 11.7 4 1 1 2.5 6.5 6.3 notes: 1. v pp /v nn = +/-90v, v dd = (v pp - v pf ) = (v nf - v nn ) = +10v 2. i sc is current into 1.0 to gnd 3. r on calculated from v out into 100 load ????????
7 hv758 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com name function v dd positive internal voltage supply (+10v). v ss power supply return (0v). v ll logic hi voltage reference input (+3.3v). g ref logic low reference, logic ground (0v). v sub substrate of the ic, all v sub pins must connect externally to the most positive potential of the ic. rgnd bleed resistors common return ground. v pp positive high voltage power supply (+90v). v nn negative high voltage power supply (-90v). v pf p-fet drive ?oating power supply, (v pp - v pf ) = +10v. v nf n-fet drive ?oating power supply, (v nf - v nn ) = +10v. txp1 output p-fet drain (open drain output) for channel 1. txn1 output n-fet drain (open drain output) for channel 1. txp2 output p-fet drain (open drain output) for channel 2. txn2 output n-fet drain (open drain output) for channel 2. txp3 output p-fet drain (open drain output) for channel 3. txn3 output n-fet drain (open drain output) for channel 3. txp4 output p-fet drain (open drain output) for channel 4. txn4 output n-fet drain (open drain output) for channel 4. pin1 input logic control of high voltage output p-fet of channel 1, hi = on, low = off. nin1 input logic control of high voltage output n-fet of channel 1, hi = on, low = off. pin2 input logic control of high voltage output p-fet of channel 2, hi = on, low = off. nin2 input logic control of high voltage output n-fet of channel 2, hi = on, low = off. pin3 input logic control of high voltage output p-fet of channel 3, hi = on, low = off. nin3 input logic control of high voltage output n-fet of channel 3, hi = on, low = off. pin4 input logic control of high voltage output p-fet of channel 4, hi = on, low = off. nin4 input logic control of high voltage output n-fet of channel 4, hi = on, low = off. en chip power enable hi=on, low=off. mc0, mc1 output current mode control pins, see drive mode control table. otp over temperature protection output, open n-fet drain, active low if ic temperature >110c. ball description ????????
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2010 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 8 hv758 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-hv758 c052710 64-ball fcbga package outline (fb) 8.00x8.00mm body, 1.97mm height (max), 0.80mm pitch symbol a a1 a2 b d d1 e e1 e sd se dimension (mm) min 1.67 0.35 1.32 0.45 7.90 5.60 bsc 7.90 5.60 bsc 0.80 bsc 0.40 bsc 0.40 bsc nom 1.82 0.40 1.42 0.50 8.00 8.00 max 1.97 0.45 1.52 0.55 8.10 8.10 drawings not to scale. supertex doc. #: dspd-64fcbgafb, version c101708. a b c d e f g h 8 7 6 5 4 3 2 1 note 1 (index area d/4 x e/4) seating plane a2 e d e d1 e1 e se sd a vi ew b a1 to p v iew side v iew bottom v iew vi ew b b note: a ball 1 identi?er must be located in the index area indicated. the ball 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. the shape of the identi?er may vary. 1. ????????
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